1. Field of the Invention
The present invention relates to a test circuit for testing the operation of functional modules (or test object circuits) such as a large scaled DRAM (Dynamic Random Access Memory) module, a CPU module, other type logic modules and small scaled memory module, and the like forming a semiconductor integrated circuit such as a LSI.
2. Description of the Related Art
One chip LSIs on which plural functional modules such as a large scaled DRAM module, a CPU module, other type logic/small scaled memory modules, and the like are mixed and mounted have been developed and manufactured.
In general, the test time required for operational test of the various functional modules mounted on the LSI is more than the sum of the test time required for each functional module. Because the various functional modules are mounted on the current one chip LSI when compared with another conventional LSI, the test time for the current one chip LSI is greater than that of the conventional LSI.
In order to reduce the total test time, it is preferred that the test operations of the functional modules mounted on the one chip LSI are executed in parallel so far as conditions permit. However, the total test time of the one chip LSI depends on the functional module that requires the maximum test time.
On the other hand, specialized testers are also used for the memory module and the logic module, respectively. It is therefore impossible to perform the test operation of the functional modules in parallel while the test operation of the large scaled DRAM is executed. On the contrary, it is also impossible to perform the test operation of the large scaled DRAM in parallel while the test operation of the functional modules is executed.
To use the specialized tester for each functional module increases the total test time of the one chip LSI. In order to eliminate this drawback, there is a method to introduce a new common tester having a common specification for the various module. However, because enormous expenses are necessary for this conventional method, the cost of the one chip LSI is thereby increased.
In general, although it is required to reduce the manufacturing cost of the LSI so far as conditions permit in spite of the type of the tester to be used, the most effective method to reduce the total cost of the manufacturing for LSI chip of the semiconductor integrated circuit is to reduce the test time of the modules mounted on the LSI chip.
FIG. 1 is a block diagram showing a test circuit performing a conventional test method for the semiconductor integrated circuit. In FIG. 1, the reference number 210 designates a semiconductor chip or a LSI chip, 211 denotes one of various kinds of modules as an object circuit for test, and 212 indicates a selector through which test results are transferred to the outside of the semiconductor chip 210.
The object circuit 211 for test can not output test results Pout [127:0]. at one time to the outside of the semiconductor chip 210 because of a pin-neck. Accordingly, the selector 212 selects test results per 32 bit and transfers them to the outside of the semiconductor chip 210. This conventional test method shown in FIG. 1 requires the test time that is four times as long as the test time in which all of the test results Pout [127:0] are transferred to the outside of the semiconductor chip 210 at one time.
The test input data In [127:0] as a test input pattern are provided to the object circuit 211 and then the output data (or test results) Out [31:0] are transferred to the outside of the semiconductor chip 210. In this case, when the combination (a, b) of both control signals a and b is (0, 0), namely (a, b)=(0, 0), the selector 212 selects the output data Pout ([127:96]. This selected output data Pout [127:96] are transferred as output data Out [31:0] to the outside of the semiconductor chip 210.
When the combination (a, b) of both control signals a and b is (0, 1), namely (a, b)=(0, 1), the selector 212 selects the output data Pout [95:64]. This selected output data Pout [95:64] are transferred as output data Out [31:0] to the outside of the semiconductor chip 210. In addition, when the combination (a, b) of both control signals a and b is (1, 0), namely (a, b)=(1, 0), the selector 212 selects the output data Pout [63:32]. This selected output data Pout [63:32] are transferred as output data Out [31:0] to the outside of the semiconductor chip 210. In the same manner, when the combination (a, b) of both control signals a and b is (1, 1), namely (a, b)=(1, 1), the selector 212 selects the output data Pout [31:0]. This selected output data Pout [31:0] are transferred as output data Out [31:0] to the outside of the semiconductor chip 210.
The output data Out [31:0] are compared with the expected data that have been prepared in advance in order to check whether the semiconductor chip 210 is a defective device or not. The output data (or the test results) Out [31:0] that are different from the expected data indicate the object circuit 211 has one or more structural defects. For example, when the output data Pout [31:0] are hxe2x80x20000 . . . 0001xe2x80x2 and the expected data are hxe2x80x20000 . . . 0000, the output data item Pout [0] is a wrong data item. Accordingly, the analysis of the failure of the semiconductor chip 210 is performed around the output data item Pout [0].
FIG. 2 is a block diagram showing a test circuit performing another conventional test method for a semiconductor integrated circuit. In FIG. 2, the reference number 211 designates the object circuit for test that has been shown in FIG. 1 as the object module for test. The reference number 220 denotes a semiconductor chip, 212 indicates a selector for selecting test results and transfer the selected test results to the outside of the semiconductor chip 220, and 223 designates a comparison circuit. The selector 212 has the same configuration of the selector 212 shown in FIG. 1.
In the conventional test method shown in FIG. 2, the test results are compared with the expected data in the semiconductor chip 220. The comparison circuit 223 comprises exclusive OR gates where the test results obtained from the object circuit 211 for test are compared with the expected data Ex [127:0].
If the object circuit 211 for test has no-defect section, the output data Pout are completely equal to the expected data EX, and the comparison circuit 223 outputs the output signal ZO=0. In this conventional test method, the external tester (not-shown) can check the presence or the absence of the defect by referring the value of the output ZO from the comparison circuit 223. Therefore because the external tester does not require the receiving operation of the output data Pout transferred from the object circuit 211 and also does not check the output data Pout four times, the conventional test method shown in FIG. 2 can reduce the test time drastically.
However, although the conventional test method shown in FIG. 2 can check the presence or the absence of the defect in the object circuit 211, it can not indicate the defect section in the object circuit 211 for test. It is impossible to specify the position of the defect in the object circuit 211 for test.
Because the conventional test circuits for the semiconductor integrated circuit have the configurations described above, the conventional test method shown in FIG. 1 can get the information for indicating the defect section in the object circuit 211 for test and has the following drawback:
When the output data Pout [31:0] obtained from the object circuit for test are not equal to the expected data, only the output data Pout [31:0] are required and other output data Pout [127:32] are not required for the analysis of the test results. Accordingly, it will be of no use to output the other output data. This conventional test method shown in FIG. 1 requires a long test time. On the other hand, although another conventional test method shown in FIG. 2 can require only the minimum test time, it can not specify the position of the defect in the object circuit.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a test circuit for a semiconductor integrated circuit capable of outputting output data (or test results including disagreement information) only for specifying the position of a defect section obtained from an object circuit for test and capable of reducing a total test time.
In accordance with one aspect of the present invention, a test circuit for a semiconductor integrated circuit, comprises a plurality of comparison means for comparing test results transferred from an object circuit for operational test of the semiconductor integrated circuit with expected data that have been prepared in advance, a plurality of control means for generating a control signal that indicates whether or not the test results are outputted to outside based on comparison results transferred from each of the plurality of comparison means, and a plurality of selection means for selecting a part of the test results based on the control signal transferred from the plurality of control means. In the test circuit, each of the plurality of comparison means, the plurality of control means, and the plurality of selection means are incorporated in the test circuit per predetermined bits, and each of the plurality of control means generates the control signal based on the comparison result that indicates only when the test results are not equal to the expected data, and outputs the generated control signal to the corresponding selection means.
In accordance with a further aspect of the preferred embodiment, each of said plurality of control means generates said control signal based on said comparison result transferred from said corresponding comparison means that indicates only when said test results corresponding to each control means are equal to said expected data and outputs said control signal to said selection means corresponding to said control means in order to output said test results to the outside.
According to another aspect of the present invention, output pins of a semiconductor chip on which the test circuit and the semiconductor integrated circuit are divided into predetermined parts, and each of the plurality of comparison means, each of the plurality of control means, and each of the plurality of selection means are assigned to each part of the divided output pins.
In accordance with another aspect of the present invention, each of the plurality of control means in the test m; circuit comprises a plurality of flip flops and a plurality of logical circuits for generating the control signal that indicates whether or not the test results are outputted to the outside based on the comparison result transferred from the corresponding comparison means and outputs the control signal to the corresponding selection means.
In accordance with another aspect of the present invention, each of the plurality of control means in the test circuit is made up of a counter circuit comprising a plurality of flip flops and a plurality of logical circuits for generating the control signal that indicates whether or not the test results are outputted to the outside based on the comparison result transferred from the corresponding comparison means and outputs the control signal to the corresponding selection means.
In this embodiment, each of the plurality of flip flops operates based on a positive edge or a negative edge of a clock signal.
In this embodiment, input and output signals each having a same level are commonly used, and input and output signals each having an opposite level to each other are used through an inverter for inverting the level of the input and output signals having the opposite level in order to have a same level in the plurality of logical circuits making up each of the plurality of control means and in order to reduce the number of said logical circuits.
In accordance with another aspect of the present invention, each of the plurality of selection means in the test circuit comprises one of a tri state buffer and a selector.
In accordance with another aspect of the present invention, each of the plurality of selection means in the test circuit comprises a tri state buffer operable based on a high enable state or a low enable state.
In accordance with another aspect of the present invention, the test circuit further comprises a second selection means for generating a control signal that indicates only a case where the test results are completely equal to the expected data, and then outputs the generated control signal to outside.